The present invention relates to a static random access memory having column decoded bit line bias.
A typical static random access memory includes an array of rows and columns of memory cells, each cell storing a data bit. During either a memory read or a memory write cycle, input row and column addresses identify the row and column of the particular memory cell with respect to which it is desired to read out or store a data bit. During a write cycle, a data input circuit receives a data bit from an external bus and passes it to the addressed memory cell for storage therein. During a data read cycle, a data output circuit receives a stored data bit from an addressed memory cell and passes it to the external bus.
Each column of memory cells uses a pair of "bit lines" to convey a data bit between cells of the column and the data input and output circuits. The polarity of bias across the bit lines represents the state of the data bit. However, gates controlled by the row address connect only one cell in each column to the column bit lines, and gates controlled by the column address connect only the bit lines of one column to the data input and output circuits. Thus, during a read or write cycle, only the memory cell residing both in the addressed row and in the addressed column is connected to a data output or input circuit and only that one cell transmits or receives a data bit via the bit lines.
Each memory cell is a relatively weak bistable latch, and when connected to the bit lines, a memory cell attempts to bias the bit lines to a polarity determined by the state of its stored bit. However, the data input circuit has a more powerful output stage, and when connected to bit lines during a write cycle, the data input circuit biases the bit lines to a polarity determined by the state of a memory input bit regardless of the state of a bit stored by the row addressed memory cell connected to the bit lines. The row addressed memory cell responds by setting the state of its stored bit to match the state of the bit line bias.
During a write cycle, the data input circuit biases only the bit lines of the addressed column. But one memory cell of each non-addressed column of the array is connected to the column bit lines during the write cycle, and each of these cells biases its column bit lines in accordance with the state of its stored bit. During a subsequent memory read cycle, the next cell connected to a pair of bit lines may have to change the polarity of the bias on those bit lines. Since the bit lines have inherent capacitance, the extra time required to charge or discharge this capacitance to overcome the bit line prebias reduces the memory access speed.
To improve memory access speed, static random access memories typically include a "precharge" circuit that temporarily clamps all bit lines to a high logic level at the end of the write cycle to remove bit line bias established during the write cycle. This enables an addressed memory cell to more quickly bias its bit lines to the appropriate state during a subsequent read cycle. However, in restoring the charge on all the bit lines of the memory, the precharge circuit produces a large current spike, particularly in large memories having many bit lines. This current spike can cause excessive noise in a memory chip and in the electronic system using the memory chip, and the current spike contributes to rated memory chip power consumption.